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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2007, zarlink semiconductor inc. all rights reserved. features ? synchronizes to 8 khz, 2.048 mhz, 8.192 mhz or 19.44 mhz input ? provides 2.048 mhz and 8.192 mhz output clocks and an 8 khz framing pulse ? automatic entry and exit from freerun mode on reference fail ? provides dpll lock and reference fail indication ? dpll bandwidth of 29 hz for all rates of input references ? less than 0.6 nsec pp intrinsic jitter on all output clocks ? 20 mhz external master clock source: clock oscillator or crystal ? simple hardware control interface applications ? synchronizer for pots slic/codec ? rate convert ntr 8 khz or gpon physical interface clock to tdm clock description the ZL30112 slic/codec dpll contains a digital phase-locked loop (dpll), which provides timing and synchronization for slic/codec devices. the ZL30112 generates tdm clock and framing signals that are phase locked to the input reference. it helps ensure system reliability by monitoring its reference for stability and by maintaining stable output clocks during short periods when the reference is unavailable. november 2007 ZL30112 slic/codec dpll data sheet figure 1 - functional block diagram reference monitor mode control state machine rst f8ko osco osci master clock ref lock dpll c2o ref_fail c8o ordering information ZL30112lde1 32 pin qfn* tubes, bake & drypack *pb free matte tin -40 c to +85 c
ZL30112 data sheet 2 zarlink semiconductor inc. 1.0 physical description 1.1 pin connections figure 2 - pin connections (32 pin 5 mm x 5 mm qfn) ZL30112 26 28 30 32 12 10 8 6 4 2 osco v dd av dd ic rst v core lock gnd agnd v dd ref f8ko ic agnd av dd c8o c2o 14 16 18 22 24 20 ic ic ic osci v core av dd av core av core agnd ic ic gnd gnd ic ref_fail 33 ic (e-pad)
ZL30112 data sheet 3 zarlink semiconductor inc. 2.0 pin description pin # name i/o type description 1 gnd ground. 0v. 2v core positive supply voltage. +1.8 v dc nominal. 3locko lock indicator (lvcmos). this output goes to a logic high when the pll is locked to a valid input reference. 4 ref_fail o reference failure indicator (lvcmos). a logic high at this output indicates that the ref input has failed. 5ico internal connection. leave unconnected. 6v core positive supply voltage. +1.8 v dc nominal. 7av core positive analog supply voltage. +1.8 v dc nominal. 8gnd ground. 0v. 9ic i internal connection. connect to gnd. 10 rst i reset (lvcmos, schmitt trigger). a logic low at this input resets the device. on power up, the rst pin must be held low for a minimum of 300 ns after the power supply pins have reached the minimum supply voltage. when the rst pin goes high, the device will transition into a reset state for 3 ms. in the reset state all outputs will be forced into high impedance. 11 osco o oscillator master clock (lvcmos). for crystal operation, a 20 mhz crystal is connected from this pin to osci. this output is not suitable for driving other devices. for clock oscillator operation, this pin must be left unconnected. 12 osci i oscillator master clock (input). for crystal operation, a 20 mhz crystal is connected from this pin to osco. for cl ock oscillator operation, this pin must be connected to a clock source. 13 ic i internal connection. connect to gnd. 14 v dd positive supply voltage. +3.3 v dc nominal. 15 av dd positive analog supply voltage. +3.3 v dc nominal. 16 gnd ground. 0v. 17 agnd analog ground. 0v. 18 av core positive analog supply voltage. +1.8 v dc nominal. 19 av dd positive analog supply voltage. +3.3 v dc nominal. 20 ic i internal connection. leave unconnected. 21 c8o o clock 8.192 mhz (lvcmos). this is a 8.192 mhz clock output. 22 agnd analog ground. 0v. 23 av dd positive analog supply voltage. +3.3 v dc nominal. 24 c2o o clock 2.048 mhz (lvcmos). this is a 2.048 mhz clock output. 25 agnd analog ground. 0v. 26 f8ko o frame pulse (lvcmos). this is an 8 khz frame pulse which marks the beginning of a 125 us frame. pulse width is 122 ns.
ZL30112 data sheet 4 zarlink semiconductor inc. 27 ref i reference input. this input is used to synchronize the pll. synchronizes to 8 khz, 2.048 mhz, 8.192 mhz or 19.44 mhz. 28 ic i internal connection. leave unconnected. 29 ic i internal connection. connect to vdd. 30 ic i internal connection. connect to vdd. 31 v dd positive analog supply voltage. +3.3 v dc nominal. 32 ic i internal connection. connect to gnd. 33 gnd ground. 0 v. package e-pad. this pin is internally connected to device gnd. it must be externally connected to gnd. pin # name i/o type description
ZL30112 data sheet 5 zarlink semiconductor inc. 3.0 functional description the ZL30112 is a slic/codec dpll providing timing (clock) and synchronization (frame) signals to network interface cards. figure 1 is a functional block diag ram which is described in the following sections. 3.1 reference monitor the input reference is monitored by two reference monito r blocks. the block diagram of reference monitoring is shown in figure 3. the reference frequency is detecte d and the clock is conti nuously monitored for two independent criteria that indi cate abnormal behavior of the reference signal, for example; loss of clock or excessive level of frequency error. to ensure proper operation of the reference monitor circuit, the minimum input pulse width restriction of 15 nsec must be observed. ? reference frequency detector (rfd) : this detector determines whether the frequency of the reference clock is 8 khz, 2.048 mhz, 8.192 mhz or 19.44 mhz and provides this information to the various monitor circuits and the phase detector circuit of the dpll. ? coarse frequency monitor (cfm) : this circuit monitors the reference frequency over intervals of approximately 30 s to quickly detect large frequency changes. ? single cycle monitor (scm) : this detector checks the period of a single clock cycle to detect large phase hits or the complete loss of the clock. figure 3 - reference monitor circuit exceeding the thresholds of any of the monitors forces the corresponding ref_fail pin to go high. the single cycle and coarse frequency failure flags force the dpll into freerun mode. reference frequency detector single cycle monitor coarse frequency monitor ref or mode select state machine dpll in freerun mode ref_fail
ZL30112 data sheet 6 zarlink semiconductor inc. 3.2 time interval error (tie) corrector circuit the tie corrector circuit eliminates p hase transients on the output clock that may occur in the course of recovery from automatic freerun mode to normal mode. on recovery from automatic freerun mode, the tie correc tor circuit measures the phase delay between the current phase (feedback signal) and the phase of the selected refer ence signal. this delay value is stored in the tie corrector circuit. this circuit creates a new virtual refere nce signal that is at the same phase position as the feedback signal. by using the virtual reference, the pl l minimizes the phase transient it experiences when it switches to another reference input or recovers from automatic freerun mode. 3.3 digital phase lock loop (dpll) the dpll of the ZL30112 consists of a phase detector, an integrated on-chip loop filt er, and a digitally controlled oscillator as shown in figure 4. the data path from the pha se detector to the filter is tapped and routed to the lock indicator that provides a lock indica tion which is output at the lock pin. figure 4 - dpll block diagram phase detector - the phase detector compares t he virtual reference signal from th e tie corrector circuit with the feedback signal and provides an error signal corresponding to the phase differ ence between the two. this error signal is passed to the loop filter circuit. loop filter - the loop filter is similar to a first order low pass filter with bandwidt h of 29 hz suitable to provide timing and synchronization for network interface cards. state select from control state machine feedback signal from frequency select mux dpll reference to frequency synthesizer virtual reference from tie corrector circuit loop filter digitally controlled oscillator phase detector lock indicator lock
ZL30112 data sheet 7 zarlink semiconductor inc. digitally controlled oscillator (dco) - the dco receives the limited and filt ered signal from the loop filter, and based on its value, generates a corresponding digital output signal. the synchroniza tion method of the dco is dependent on the state of the ZL30112. in normal mode, the dco provides an output signal which is frequency and phase locked to the selected input reference signal. in the automatic freerun mode, the dco is free running at a frequency equal to the frequency that the dco was generating in normal mode. lock indicator - the lock detector monitors if the output value of the phase detector is within the phase-lock- window for a certain time. the select ed phase-lock-window guarantees the stabl e operation of the lock pin with maximum network jitter and wander on the reference input. if the dpll goes into the automatic freerun mode, the lock pin will initially stay high for 0.1 s. if at that poi nt the dpll is still in the automatic freerun mode, the lock pin will go low. 3.4 frequency synthesizers the output of the dco is used by the frequency synthesizers to generate the ou tput clocks and frame pulses which are synchronized to the input reference (ref). the frequency synthesizer uses digital techniques to generate output clocks and advanced noise shaping techniques to minimize the output jitt er. the clock and frame pulse outputs have limited drive capability and should be buffered when driving high capacitance loads. 3.5 master clock the ZL30112 can use either a clock or crystal as the master timing source. for recommended master timing circuits, see the applications - master clock section.
ZL30112 data sheet 8 zarlink semiconductor inc. 4.0 modes of operation figure 5 - modes of operation normal mode in normal mode, the ZL30112 provides timing and fram e synchronization signals which are synchronized to the reference input (ref). the input re ference signal may have a nominal frequency of 8 khz, 2.048 mhz, 8.192 mhz, or 19.44 mhz. the frequency of the re ference inputs are automatically det ected by the reference monitors. automatic freerun mode automatic freerun mode is typically used for short durati ons while system synchronization is temporarily disrupted. in automatic freerun mode, the zl3011 2 provides timing and synchronization signals, which are not locked to an external reference signal, but are based on the freerun accuracy of the external oscillator. 5.0 measures of performance the following are some pll performance indi cators and their corresponding definitions. 5.1 jitter generation (intrinsic jitter) timing jitter is defined as the high frequency variation of the clock edges from their ideal positions in time. wander is defined as the low-frequency variation of the clock e dges from their ideal positions in time. high and low frequency variation imply phase oscillation frequencies re lative to some demarcation frequency. (often 10 hz or 20 hz for ds1 or e1, higher for sonet/sdh clocks.) jitter parameters given in this data sheet are total timing jitter numbers, not cycle-to-cycle jitter. 5.2 jitter tolerance jitter tolerance is a measure of the ability of a pll to oper ate properly (i.e., remain in lock and or regain lock in the presence of large jitter magnitudes at various jitter frequencie s) when jitter is applied to its reference. the applied jitter magnitude and jitter frequency depends on the applicable standards. ref_dis=1: current selected reference disrupted (see figure 3) tie correction freerun ref_dis=0 ref_dis=1 ref_dis=0 ref_dis=1 rst normal (locked)
ZL30112 data sheet 9 zarlink semiconductor inc. 5.3 jitter transfer jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter at the input of the device. i nput jitter is applied at va rious amplitudes and frequencies, and output jitter is measured with various filters depending on the applicable standards . for the ZL30112, the internal low pass loop filter determines the jitter attenuation. since intrinsic jitter is always present, jitter attenuation will appear to be lowe r for small input jitter signals than for large ones. consequently, accurate jitter transfer functi on measurements are usually made with large input jitter signals (for example 75% of the spec ified maximum tolerable input jitter). 5.4 freerun accuracy frequency accuracy is defined as the absolute accuracy of an output clock signal when it is not locked to an external reference, but is operating in a free running mo de. for the ZL30112, the freerun accuracy is equal to the master clock (osci) accuracy. 5.5 capture range also referred to as pull-in range. this is the input fr equency range over which the pll must be able to pull into synchronization. the ZL30112 capture range is equal to 130 ppm minus the accuracy of the master clock (osci). for example, a +32 ppm master clock results in a capt ure range of +162 ppm on one side and -98 ppm on the other side of frequency range. 5.6 lock range this is the input frequency range over which the synchronizer must be able to maintain synchronization. the lock range is equal to the capture range for the ZL30112. 5.7 time interval error (tie) tie is the time delay between a given ti ming signal and an ideal timing signal. 5.8 maximum time interval error (mtie) mtie is the maximum peak to peak delay between a give n timing signal and an ideal timing signal within a particular observation period. 5.9 phase continuity phase continuity is the phase difference between a given timi ng signal and an ideal timing signal at the end of a particular observation period. usually, the given timing signal and the ideal timing signal are of the same frequency. phase continuity applies to the output of the pll after a signal disturbance due to a reference switch or a mode change. the observation period is usually t he time from the disturbance, to just after the synchronizer has settled to a steady state.
ZL30112 data sheet 10 zarlink semiconductor inc. 5.10 phase lock time this is the time it takes the pll to phase lock to the input signal. phase lock occurs when the input signal and output signal are aligned in phase with respect to each othe r within a certain phase distance (not including jitter). lock time is affected by many factors which include: ? initial input to output phase difference ? initial input to output frequency difference ? pll loop filter bandwidth ? in-lock phase distance the presence of input jitter makes it difficult to define when the pll is locked as it may not be able to align its output to the input within the required phase distance, dependen t on the pll bandwidth and the input jitter amplitude and frequency. although a short lock time is desirable, it is not always possible to achiev e due to other synchronizer requirements. for instance, better jitter transfer performance is achi eved with a lower frequency loop filter which increases lock time. see section 7.2, ?performance characteristics? for maximum phase lock time. 6.0 applications this section contains ZL30112 application specific details for power supply decoupling, clock and crystal operation, reset operation, and control operation. 6.1 power supply decoupling jitter levels on the ZL30112 output clocks may increase if the device is exposed to excessive noise on its power pins. for optimal jitter performance, the ZL30112 device s hould be isolated from noise on power planes connected to its 3.3 v and 1.8 v supply pins. for recommended common layout practices, refer to zarlink application note zlan-178. 6.2 master clock the ZL30112 can use either a clock or cr ystal as the master timing source. za rlink application note zlan-68 lists a number of applicable oscillators and cr ystals that can be us ed with the ZL30112. 6.2.1 clock oscillator when selectin g a clock oscillator, numerous pa rameters must be considered. th ese includes abso lute frequency, frequency change over temperature, output rise and fa ll times, output levels, duty cycle and phase noise. 1 frequency 20 mhz 2 tolerance as required 3rise & fall time <10ns 4 duty cycle 40% to 60% table 1 - typical clock oscillator specification
ZL30112 data sheet 11 zarlink semiconductor inc. the output clock should be connected directly (not ac co upled) to the osci input of the ZL30112 and the osco output should be left open as shown in figure 6. figure 6 - clock os cillator circuit 6.2.2 crystal oscillator alternatively, a crystal oscillator may be used. a complete oscillator circuit made up of a crystal, resistor and capacitors is shown in figure 7. the accuracy of a crystal oscillator depends on the cryst al tolerance as well as the load capacitance tolerance. typically, for a 20 mhz crystal specified with a 32 pf load capacitance, each 1 pf change in load capacitance contributes approximately 9 ppm to the frequency deviation. consequent ly, capacitor tolerances and stray capacitances have a major effect on the accuracy of the oscillator frequency. the crystal should be a fundamental mode type - not an over tone. the fundamental mode crystal permits a simpler oscillator circuit with no additional fi lter components and is less likely to generate spurious responses. the crystal specification is as follows. 1 frequency 20 mhz 2 tolerance as required 3 oscillation mode fundamental 4 resonance mode parallel 5 load capacitance as required 6 maximum series resistance 50 ? table 2 - typical crystal oscillator specification +3.3 v 20 mhz out gnd 0.1 f +3.3 v osco ZL30112 osci no connection
ZL30112 data sheet 12 zarlink semiconductor inc. figure 7 - crystal oscillator circuit 6.3 power up sequence the ZL30112 requires that the 3.3 v is not powered after the 1.8 v. this is to pr event the risk of latch-up due to the presence of parasitic diodes in the io pads. two options are given: 1. power-up 3.3 v first, 1.8 v later 2. power up 3.3 v and 1.8 v simultaneously ensuring that the 3.3 v power is never lower than 1.8 v minus a few hundred millivolts (e.g., by using a schottky diode or controlled slew rate) 6.4 reset circuit a simple power up reset circuit with about a 60 s reset low time is shown in figure 8. resistor r p is for protection only and limits current into the rst pin during power down conditions. the re set low time is not critical but should be greater than 300 ns. figure 8 - power-up reset circuit osco 1 m ? 20 mhz ZL30112 osci 100 ? 1 h the 100 ? resistor and the 1 h inductor may improve stability and are optional. +3.3 v rst r p 1 k ? c 10 nf r 10 k ? ZL30112
ZL30112 data sheet 13 zarlink semiconductor inc. 7.0 characteristics 7.1 ac and dc electr ical characteristics * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. * voltages are with respect to ground (gnd) unless otherwise stated. * voltages are with respect to ground (gnd) unless otherwise stated. absolute maximum ratings* parameter symbol min. max. units 1 supply voltage v dd_r -0.5 4.6 v 2 core supply voltage v core_r -0.5 2.5 v 3 voltage on any digital pin v pin -0.5 6 v 4 voltage on osci and osco pin v osc -0.3 v dd + 0.3 v 5 current on any pin i pin 30 ma 6 storage temperature t st -55 125 c 7 package power dissipation p pd 195 mw 8esd rating v esd 2k v recommended operating conditions* characteristics sym. min. typ. max. units 1 supply voltage v dd 2.97 3.30 3.63 v 2 core supply voltage v core 1.62 1.80 1.98 v 3 operating temperature t a -40 25 85 c dc electrical characteristics* characteristics sym. min. max. units notes 1 supply current with: osci = 0 v i dds 2.5 7.0 ma outputs loaded with 30 pf 2osci = clocki dd 43 ma outputs unloaded 3 core supply current with: osci = 0 v i cores 20 ua 4osci = clocki cores 18 ma 5 schmitt trigger low to high threshold point v cih 1.43 1.85 v all device inputs are schmitt trigger type. 6 schmitt trigger high to low threshold point v cil 0.8 1.1 v 7 input leakage current i il -105 105 a v i =v dd or 0 v
ZL30112 data sheet 14 zarlink semiconductor inc. * supply voltage and operating temperature are as per recommended operating conditions. * voltages are with respect to ground (gnd) unless otherwise stated. * supply voltage and operating temperature are as per recommended operating conditions. * voltages are with respect to ground (gnd) unless otherwise stated. figure 9 - timing parameter measurement voltage levels. 8 high-level output voltage v oh 2.4 v i oh = 8 ma for clock and frame- pulse outputs, 4ma for status outputs 9 low-level output voltage v ol 0.4 v i ol = 8 ma for clock and frame- pulse outputs, 4ma for status outputs ac electrical charact eristics* - timing parameter measuremen t voltage levels (see figure 9). characteristics sym. cmos units 1 threshold voltage v t 1.5 v 2 rise and fall threshold voltage high v hm 2.0 v 3 rise and fall threshold voltage low v lm 0.8 v dc electrical characteristics* characteristics sym. min. max. units notes t irf, t orf timing reference points all signals v hm v t v lm t irf, t orf
ZL30112 data sheet 15 zarlink semiconductor inc. * supply voltage and operating temperature are as per recommended operating conditions. * period min/max values are the limits to avoid a single-cycle fault detection. short-term and long-term average periods must b e within out-of- range limits. * supply voltage and operating temperature are as per recommended operating conditions and 30 pf load. figure 10 - output timing referenced to f8o ac electrical character istics* - input timing reference ref (see figure 11). characteristics symbol min. typ. max. units 1 8 khz reference period t ref8kp 120 125 128 s 2 2.048 mhz reference period t ref2p 263 488 712 ns 3 8.192 mhz reference period t ref8p 63 122 175 ns 4 19.44 mhz reference period t ref8kp 38 51 75 ns 5 reference pulse width high or low t refw 15 ns ac electrical char acteristics* - output timing (see figure 10) characteristics sym. min. max. units notes 1 f8o pulse width high t f8h 121 124 ns 2 c2o pulse width low t c2l 243 245 ns 3 c2o delay t c2d -1.0 1.0 ns 4 c8o pulse width low t c8l 60 62 ns 5 c8o delay t c8d -1.0 1.0 ns 6 output clock and frame pulse rise time t or 1.0 2.0 ns 7 output clock and frame pulse fall time t of 1.0 2.5 ns t f8h f8o c8o c2o t c8d t c8l t c2l t c2d
ZL30112 data sheet 16 zarlink semiconductor inc. * supply voltage and operating temperature are as per recommended operating conditions. figure 11 - input to output timing * supply voltage and operating temperature are as per recommended operating conditions. ac electrical character istics* - input to out put timing for reference ref (see figure 11). characteristics symbol min. max. units 1 8 khz reference input to f8ko delay t ref8kd -0.3 2 ns 2 2.048 mhz reference input to f8ko delay t ref2_f8kd -1.1 0.9 ns 3 8.192 mhz reference input to f8ko delay t ref8_f8kd -0.6 0.8 ns 4 19.44 mhz reference input to f8ko delay t ref19_f8kd -1.7 1 ns ac electrical characteristics* - osci 20 mhz master clock input characteristics sym. min. typ. max. units notes 1 oscillator tolerance -32 +32 ppm 2 duty cycle 40 60 % 3 rise time 10 ns 4 fall time 10 ns ref t refp t ref8d , t ref_f8kd t refw t refd t refw f8ko output clock with the same frequency as ref
ZL30112 data sheet 17 zarlink semiconductor inc. 7.2 performance characteristics * supply voltage and operating temperature are as per recommended operating conditions. ** lock time represent time to achieve phase/frequency lock and it excludes time to pull-in the input to output phase differenc e. * supply voltage and operating temperature are as per recommended operating conditions. performance characteristics* - functional characteristics min. typ. max. units notes 1 freerun stability na ppm determined by stability of the 20 mhz master clock oscillator 2 capture range -130 +130 ppm the 20 mhz master clock oscillator set at 0.ppm lock time** 329hz filter 1 s output phase continuity (mtie) 4 switching from normal mode to automatic freerun mode 0ns 5 switching from automatic freerun mode to normal mode 13 ns performance characteristics* - unfiltered intrinsic jitter signal max. [ns pp ] notes 1 c2o 0.6 2 c8o 0.6 3 f8ko (8 khz) 0.6
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